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ht82k68e-l/ht82k68a-l multimedia keyboard encoder 8-bit mcu rev. 1.40 1 february 1, 2011 features operating voltage: 1.8v~5.5v 34 bidirectional i/o line and 3 cmos output one 8-bit programmable timer counter with overflow interrupts crystal or rc oscillator watchdog timer 3k 16 program eprom 160 8 data ram one external interrupt pin (shared with pc2) 2.0v lvr by option (default disable) halt function and wake-up feature reduce power consumption six-level subroutine nesting bit manipulation instructions 16-bit table read instructions 63 powerful instructions all instructions in 1 or 2 machine cycles 20/28-pin sop, 32-pin qfn and 48-pin ssop/lqfp packages general description this device is an 8-bit high performance peripheral in - terface ic, designed for multiple i/o products and multi - media applications. it supports interface to a low speed pc with multimedia keyboard or wireless keyboard in windows 95, windows 98 or windows 2000 environ - ment. a halt feature is included to reduce power con - sumption. the mask version ht82k68a-l is fully pin and functionally compatible with the otp version ht82k68e-l device.
block diagram ht82k68e-l/ht82k68a-l rev. 1.40 2 february 1, 2011

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pin assignment pin description pin name i/o mask option description pa0~pa7 i/o wake-up pull-high or none bidirectional 8-bit input/output port. each bit can be configured as a wake-up input by mask option. software* instructions determine the cmos output or schmitt trigger input with or without 12k pull-high resistor. pb0~pb7 i/o pull-high or none bidirectional 8-bit input/output port. software* instructions determine the output or schmitt trigger input with or without pull-high resistor. pc0 i/o wake-up pull-high or none this pin is an i/o port. nmos open drain output with pull-high resistor and can be used as data or clock line of ps2. this pin can be configured as a wake-up input by mask option. pc1 i/o wake-up pull-high or none this pin is an i/o port. nmos open drain output with pull-high resistor and can be used as data or clock line of ps2. this pin can be configured as a wake-up input by mask option. pc2~pc3 i/o wake-up pull-high or none bidirectional 2-bit input/output port. each bit can be configured as a wake-up input by mask option. software* instructions determine the cmos output or schmitt trigger input with or without pull-high resistor. pc2 also as external interrupt input pin. pe0 determine whether rising edge or falling edge of pc2 to trigger the int circuit. pc4~pc7 i/o pull-high or none bidirectional 4-bit input/output port. software* instructions determine the cmos output or schmitt trigger input with or without pull-high resistor. pd0~pd7 i/o pull-high or none bidirectional 8-bit input/output port. software* instructions determine the cmos output or schmitt trigger input with or without pull-high resistor. ht82k68e-l/ht82k68a-l rev. 1.40 3 february 1, 2011 2 5 2 ) " - " 4 " 5 " ) - 6 $ 7 3 ) 5 4 - 3

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pin name i/o mask option description pe0~pe1 i/o pull-high or none bidirectional input/output port. software* instruction determine the cmos output or schmitt trigger input with or without pull-high resistor. if pe0 output 1, rising edge of pc2 trigger int circuit. pe0 output 0, falling edge of pc2 trigger int circuit. pe2 o this pin is a cmos output structure. the pad can function as led (scr) drivers for the keyboard. i ol =18ma at v ol =3.4v pe3 o this pin is a cmos output structure. the pad can function as led (num) drivers for the keyboard. i ol =18ma at v ol =3.4v pe4 o this pin is a cmos output structure. the pad can function as led (cap) drivers for the keyboard. i ol =18ma at v ol =3.4v vdd positive power supply vss negative power supply, ground res i chip reset input. active low. built-in power-on reset circuit to reset the entire chip. chip can also be externally reset via res pin osc1 osc2 i o crystal or rc osc1, osc2 are connected to an rc network or a crystal for the internal system clock. in the case of rc operation, osc2 is the output terminal for the 1/4 system clock; a 110k resistor is connected to osc1 to generate a 2 mhz frequency. note: *: software means the ht ide (holtek integrated development environment) can be configured by mask option. absolute maximum ratings supply voltage ..........................v ss 0.3v to v ss +6.0v storage temperature ........................... 50 cto125 c input voltage .............................v ss 0 . 3v to v dd +0.3v operating temperature .......................... 25 cto70 c note: these are stress ratings only. stresses exceeding the range specified under absolute maximum ratings may cause substantial damage to the device. functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability. d.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions v dd operating voltage 1.8 5.5 v i dd1 operating current (crystal osc) 3v no load, f sys = 6mhz 0.7 1.5 ma 5v 25ma i dd2 operating current (rc osc) 3v no load, f sys = 6mhz 0.5 1.5 ma 5v 25ma i stb1 standby current (wdt enabled) 3v no load, system halt 8 a 5v 15 a i stb2 standby current (wdt disabled) 3v no load, system halt 3 a 5v 6 a v il1 input low voltage for i/o ports (schmitt) 3v 0 0.3v dd v 5v 0 0.3v dd v v ih1 input high voltage for i/o ports (schmitt) 3v 0.7v dd v dd v 5v 0.7v dd v dd v ht82k68e-l/ht82k68a-l rev. 1.40 4 february 1, 2011
symbol parameter test conditions min. typ. max. unit v dd conditions v il2 input low voltage (reset ) 3v 0 0.7 v 5v 0 1.3 v v ih2 input high voltage (reset ) 3v 0.9v dd v dd v 5v 0.9v dd v dd v v lvr low voltage reset 2.0 v i ol i/o port sink current of pa, pb, pc, pd, pe0~1 5v v ol = 0.1v dd 24 ma i oh i/o port source current of pa, pb, pc, pd, pe0~4 5v v oh = 0.9v dd 2.5 4 ma i led led sink current (scr, num, cap) 5v v ol =3.4v 10 17 25 ma t por power-on reset time 5v r=100k , c=0.1 f 50 100 150 ms r ph internal pull-high resistance of pa, pb, pc, pd, pe port 3v 30 60 90 k 5v 15 30 45 k r ph1 internal pull-high resistance of data, clk 3v 4915 k 5v 2 4.7 8 k
f/f frequency variation 5v crystal 1 %
f/f1 frequency variation 5v rc 20 % a.c. characteristics ta=25 c symbol parameter test conditions min. typ. max. unit v dd conditions f sys1 system clock (crystal osc) 1.8v 450 4000 khz 5v 450 8000 khz f sys2 system clock (rc osc) 3v 450 6000 khz 5v 450 8000 khz t wdtosc watchdog oscillator period 3v 45 90 180 s 5v 35 78 130 s t wdt1 watchdog time-out period (rc) 3v without wdt prescaler 12 23 45 ms 5v 9 19 35 ms t wdt2 watchdog time-out period (system clock) without wdt prescaler 1024 t sys t res external reset low pulse width 1 s t sst system start-up timer period power-up or wake-up from halt 1024 t sys t int interrupt pulse width 1 s note: t sys = 1/f sys1 or 1/f sys2 ht82k68e-l/ht82k68a-l rev. 1.40 5 february 1, 2011
mode program counter 11 10 9 8 7 6 5 4 3 2 1 0 initial reset 000000000000 external interrupt 000000000100 timer counter overflow 000000001000 skip program counter+2 loading pcl 11 10 9 8 @7 @6 @5 @4 @3 @2 @1 @0 jump, call branch #11 #10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0 return from subroutine s11 s10 s9 s8 s7 s6 s5 s4 s3 s2 s1 s0 ht82k68e-l/ht82k68a-l rev. 1.40 6 february 1, 2011 3 - 3 - 3 - 9 % ' ' 6 7 : ' ' 6 ; 7 9 % ' ' 6 < 7 : ' ' 6 7 9 % ' ' 6 < 7 : ' ' 6 < 7 < < # ' / = ' 6 '
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' 7 execution flow functional description execution flow the device system clock is derived from either a crystal or an rc oscillator. the system clock is internally di - vided into four non-overlapping clocks. one instruction cycle consists of four system clock cycles. instruction fetching and execution are pipelined in such a way that a fetch takes one instruction cycle while de - coding and execution takes the next instruction cycle. however, the pipelining scheme causes each instruc - tion to effectively execute within one cycle. if an instruc - tion changes the program counter, two cycles are required to complete the instruction. program counter pc the 12-bit program counter (pc) controls the sequence in which the instructions stored in the program rom are executed and its contents specify a maximum of 4096 addresses. after accessing a program memory word to fetch an in - struction code, the contents of the program counter are incremented by one. the program counter then points to the memory word containing the next instruction code. when executing a jump instruction, conditional skip ex - ecution, loading pcl register, subroutine call, initial re - set, internal interrupt, external interrupt or return from subroutine, the pc manipulates the program transfer by loading the address corresponding to each instruction. the conditional skip is activated by instruction. once the condition is met, the next instruction, fetched during the current instruction execution, is discarded and a dummy cycle replaces it to get the proper instruction. otherwise proceed with the next instruction. the lower byte of the program counter (pcl) is a read - able and writeable register (06h). moving data into the pcl performs a short jump. the destination will be within 256 locations. once a control transfer takes place, an additional dummy cycle is required. program memory rom the program memory is used to store the program in - structions which are to be executed. it also contains data, table, and interrupt entries, and is organized with 3072 16 bits, addressed by the program counter and ta - ble pointer. note: *11~*0: program counter bits #11~#0: instruction code bits s11~s0: stack register bits @7~@0: pcl bits
instruction(s) table location 11 10 9 8 7 6 5 4 3 2 1 0 tabrdc [m] p11 p10 p9 p8 @7 @6 @5 @4 @3 @2 @1 @0 tabrdl [m] 1011@7@6@5@4@3@2@1@0 ht82k68e-l/ht82k68a-l rev. 1.40 7 february 1, 2011 certain locations in the program memory are reserved for special usage: location 000 this area is reserved for the initialization program. after chip reset, the program always begins execution at location 000h. location 004h location 004h is reserved for external interrupt service program. if the pc2 (external input pin) is activated, the interrupt is enabled, and the stack is not full, the program begins execution at location 004h. the pin pe0 determine whether the rising or falling edge of the pc2 to activate external interrupt service program. location 008h this area is reserved for the timer counter interrupt service program. if timer interrupt results from a timer counter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008h. table location any location in the rom space can be used as look-up tables. the instructions tabrdc [m] (the current page, one page=256 words) and tabrdl [m] (the last page) transfer the contents of the lower-order byte to the specified data memory, and the higher-order byte to tblh (08h). only the destination of the lower-order byte in the table is well-defined, the other bits of the table word are transferred to the lower portion of tblh, the remaining 1 bit is read as 0. the table higher-order byte register (tblh) is read only. the tblh is read only and cannot be restored. if the main routine and the isr (interrupt service routine) both employ the table read instruction, the contents of the tblh in the main routine are likely to be changed by the table read instruction used in the isr. errors can occur. in other words, using the table read instruction in the main routine and the isr simultaneously should be avoided. however, if the table read instruction has to be applied in both the main routine and the isr, the interrupt is supposed to be disabled prior to the table read instruction. it will not be enabled until the tblh has been backed up. the table pointer (tblp) is a read/write register (07h), which indicates the table location. before accessing the table, the location must be placed in tblp. all table related instructions need 2 cycles to complete the operation. these areas may function as normal program memory depending upon the requirements. stack register stack this is a special part of the memory which is used to save the contents of the program counter (pc) only. the stack is organized into six levels and is neither part of the data nor part of the program space, and is neither readable nor writeable. the activated level is indexed by the stack pointer (sp) and is neither readable nor writeable. at a subroutine call or interrupt acknowledge- ment, the contents of the program counter are pushed onto the stack. at the end of a subroutine or an interrupt routine, signaled by a return instruction (ret or reti), the program counter is restored to its previous value from the stack. after a chip reset, the sp will point to the top of the stack. data memory ram the data memory is designed with 184 8 bits. it is di - vided into two functional groups: special function regis - ters and general purpose data memory (160 8). most of them are read/write, but some are read only. the unused space before 60h is reserved for future ex - panded usage and reading these locations will get the result 00h. the general purpose data memory, ad - dressed from 60h to ffh, is used for data and control information under instruction command. all data mem - ory areas can handle arithmetic, logic, increment, dec - rement and rotate operations directly. except for some dedicated bits, each bit in the data memory can be set > ? '
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ht82k68e-l/ht82k68a-l rev. 1.40 8 february 1, 2011 and reset by the set [m].i and clr [m].i instructions, re - spectively. they are also indirectly accessible through memory pointer registers (mp0;01h, mp1;03h). indirect addressing register location 00h and 02h are indirect addressing registers that are not physically implemented. any read/write op - eration of [00h] and [02h] can access the data memory pointed to by mp0 (01h) and mp1 (03h) respectively. reading location 00h or 02h indirectly will return the re - sult 00h. writing indirectly results in no operation. the function of data movement between two indirect ad - dressing registers is not supported. the memory pointer registers, mp0 and mp1, are 8-bit registers which can be used to access the data memory by combining corre - sponding indirect addressing registers. accumulator the accumulator is closely related to the alu opera - tions. it is also mapped to location 05h of the data mem - ory and is capable of carrying out immediate data operations. the data movement between two data memory locations must pass through the accumulator. arithmetic and logic unit alu this circuit performs 8-bit arithmetic and logic operation. the alu provides the following functions: arithmetic operations (add, adc, sub, sbc, daa) logic operations (and, or, xor, cpl) rotation (rl, rr, rlc, rrc) increment and decrement (inc, dec) branch decision (sz, snz, siz, sdz ....) the alu not only saves the results of a data operation but also changes the status register. status register status the 8-bit status register (0ah) contains the zero flag (z), carry flag (c), auxiliary carry flag (ac), overflow flag (ov), power down flag (pdf) and watch dog time-out flag (to). the status register not only records the status information but also controls the operation sequence. with the exception of the to and pdf flags, bits in the status register can be altered by instructions like most other registers. any data written into the status register will not change the to or pdf flags. it should be noted that operations related to the status register may give different results from those intended. the to and pdf flags can only be changed by system power up, watch- dog timer overflow, executing the halt instruction and clearing the watchdog timer. the z, ov, ac and c flags generally reflect the status of the latest operations. in addition, on entering an interrupt sequence or execut - ing a subroutine call, the status register will not be auto - matically pushed onto the stack. if the contents of status are important and if the subroutine can corrupt the sta - tus register, precaution must be taken to save it prop - erly.
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ht82k68e-l/ht82k68a-l rev. 1.40 9 february 1, 2011 interrupt the device provides an internal timer counter interrupt and an external interrupt shared with pc2. the interrupt control register (intc;0bh) contains the interrupt control bits to set not only the enable/disable status but also the interrupt request flags. once an interrupt subroutine is serviced, all other inter - rupts will be blocked (by clearing the emi bit). this scheme may prevent any further interrupt nesting. other interrupt requests may occur during this interval but only the interrupt request flag is recorded. if a certain inter- rupt requires servicing within the service routine, the emi bit and the corresponding bit of the intc may be set to allow interrupt nesting. if the stack is full, the inter- rupt request will not be acknowledged, even if the re- lated interrupt is enabled, until the sp is decremented. if immediate service is desired, the stack must be pre - vented from becoming full. all these kinds of interrupt have the wake-up capability. as an interrupt is serviced, a control transfer occurs by pushing the program counter onto the stack followed by a branch to a subroutine at the specified location in the program memory. only the program counter is pushed onto the stack. if the contents of the register and status register (status) are altered by the interrupt service program which corrupt the desired control sequence, the contents should be saved in advance. the internal timer counter interrupt is initialized by set - ting the timer counter interrupt request flag (t0f; bit 5 of intc), which is normally caused by a timer counter overflow. when the interrupt is enabled, and the stack is not full and the t0f bit is set, a subroutine call to location 08h will occur. the related interrupt request flag (t0f) will be reset and the emi bit cleared to disable further in- terrupts. the external interrupt is shared with pc2. the external interrupt is activated, the related interrupt request flag (eif; bit4 of intc) is then set. when the interrupt is en- abled, the stack is not full, and the external interrupt is active, a subroutine call to location 04h will occur. the interrupt request flag (eif) and emi bits will also be cleared to disable other interrupts. the external interrupt (pc2) can be triggered by a high to low transition, or a low to high transition of the pc2, which is dependent on the output level of the pe0. when pe0 is output high, the external interrupt is trig - gered by a low to high transition of the pc2. when pe0 is output low, the external interrupt is triggered by a high to low transition of pc2. bit no. label function 0c c is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise c is cleared. c is also affected by a rotate through carry instruction. 1ac ac is set if an operation results in a carry out of the low nibbles in addition or if no borrow from the high nibble into the low nibble in subtraction; otherwise ac is cleared. 2 z z is set if the result of an arithmetic or logical operation is zero; otherwise z is cleared. 3ov ov is set if an operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise ov is cleared. 4 pdf pdf is cleared when either a system power-up or executing the clr wdt instruction. pdf is set by executing a halt instruction. 5to to is cleared by a system power-up or executing the clr wdt or halt instruction. to is set by a wdt time-out. 6, 7 unused bit, read as 0 status (0ah) register bit no. label function 0 emi controls the master (global) interrupt (1= enabled; 0= disabled) 1 eei control the external interrupt 2 et0i controls the timer counter interrupt (1= enabled; 0= disabled) 3 unused bit, read as 0 4 eif external interrupt flag 5 t0f internal timer counter request flag (1= active; 0= inactive) 6, 7 unused bit, read as 0 intc (0bh) register
ht82k68e-l/ht82k68a-l rev. 1.40 10 february 1, 2011 during the execution of an interrupt subroutine, other in - terrupt acknowledgements are held until the reti in - struction is executed or the emi bit and the related interrupt control bit are set to 1 (if the stack is not full). to return from the interrupt subroutine, a ret or reti in - struction may be invoked. reti will set the emi bit to en - able an interrupt service, but ret will not. interrupts occurring in the interval between the rising edges of two consecutive t2 pulses, will be serviced on the latter of the two t2 pulses, if the corresponding interrupts are enabled. in the case of simultaneous re - quests, the following table shows the priority that is ap - plied. these can be masked by resetting the emi bit. interrupt source vector external interrupt 1 04h timer counter overflow 08h once the interrupt request flags (t0f) are set, they will remain in the intc register until the interrupts are ser - viced or cleared by a software instruction. it is suggested that a program does not use the call subroutine within the interrupt subroutine. because interrupts often occur in an unpredictable manner or need to be serviced immediately in some applications, if only one stack is left and enabling the interrupt is not well controlled, once the call subroutine operates in the interrupt subroutine it will damage the original con- trol sequence. oscillator configuration there are two oscillator circuits in the microcontroller. both are designed for system clocks; the rc oscillator and the crystal oscillator, which are determined by mask options. no matter what oscillator type is selected, the signal provides the system clock. the halt mode stops the system oscillator and resists the external signal to conserve power. if an rc oscillator is used, an external resistor between osc1 and vdd is needed and the resistance must range from 20k to 510k . the system clock, divided by 4, is available on osc2, which can be used to syn - chronize external logic. the rc oscillator provides the most cost effective solution. however, the frequency of the oscillation may vary with vdd, temperature and the chip itself due to process variations. it is, therefore, not suitable for timing sensitive operations where accurate oscillator frequency is desired. if the crystal oscillator is used, a crystal across osc1 and osc2 is needed to provide the feedback and phase shift needed for oscillator, no other external components are needed. instead of a crystal, the resonator can also be connected between osc1 and osc2 to get a fre - quency reference, but two external capacitors in osc1 and osc2 are required. the wdt oscillator is a free running on-chip rc oscilla - tor, and no external components are required. even if the system enters the power down mode, the system clock is stopped, but the wdt oscillator still works for a period of approximately 78 s. the wdt oscillator can be disabled by mask option to conserve power. watchdog timer wdt the wdt clock source is implemented by a dedicated rc oscillator (wdt oscillator) or instruction clock (sys- tem clock divided by 4), decided by mask options. this timer is designed to prevent a software malfunction or se- quence jumping to an unknown location with unpredict- able results. the watchdog timer can be disabled by mask option. if the watchdog timer is disabled, all the ex- ecutions related to the wdt results in no operation. once the internal wdt oscillator (rc oscillator normally with a period of 78 s) is selected, it is first divided by 256 (8-stages) to get the nominal time-out period of approxi - mately 20ms. this time-out period may vary with temper - ature, vdd and process variations. by invoking the wdt prescaler, longer time-out periods can be realized. writ - ing data to ws2, ws1, ws0 (bit 2,1,0 of the wdts) can give different time-out periods. if ws2, ws1, ws0 are all equal to 1, the division ratio is up to 1:128, and the maxi - mum time-out period is 2.6 seconds. # ' / = , - 0 ; 1 '
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ht82k68e-l/ht82k68a-l rev. 1.40 11 february 1, 2011 if the wdt oscillator is disabled, the wdt clock may still come from the instruction clock and operate in the same manner except that in the halt state the wdt may stop counting and lose its protecting purpose. in this situation the wdt logic can be restarted by external logic. the high nibble and bit 3 of the wdts are reserved for user defined flags, which can be used to indicate some speci - fied status. if the device operates in a noisy environment, using the on-chip rc oscillator (wdt osc) is strongly recom - mended, since the halt will stop the system clock. ws2 ws1 ws0 division ratio 000 1:1 001 1:2 010 1:4 011 1:8 1 0 0 1:16 1 0 1 1:32 1 1 0 1:64 1 1 1 1:128 wdts (09h) register the wdt overflow under normal operation will initialize chip reset and set the status bit to. an overflow in the halt mode, initializes a warm reset only when the pro - gram counter and stack pointer are reset to zero. to clear the contents of the wdt (including the wdt prescaler ), three methods are adopted; external reset (a low level to reset ), software instruction(s), or a halt instruction. there are two types of software instructions; clr wdt and clr wdt1/clr wdt2. of these two types of instruction, only one can be active depending on the mask option clr wdt times selection option . if the clr wdt is selected (ie. clr wdt times equal one), any execution of the clr wdt instruction will clear the wdt. in case clr wdt1 and clr wdt2 are chosen (ie. clrwdt times equal two), these two in - structions must be executed to clear the wdt; otherwise, the wdt may reset the chip because of the time-out. power down operation halt the halt mode is initialized by the halt instruction and results in the following... the system oscillator will turn off but the wdt oscillator keeps running (if the wdt oscillator is selected). the contents of the on?chip ram and registers remain unchanged. wdt and wdt prescaler will be cleared and recount again (if the wdt clock has come from the wdt oscillator). all i/o ports maintain their original status. the pdf flag is set and the to flag is cleared. the system can leave the halt mode by means of an external reset, interrupt, and external falling edge signal on port a and port c [0:3] or a wdt overflow. an exter - nal reset causes a device initialization and the wdt overflow performs a warm reset . examining the to and pdf flags, the reason for chip reset can be deter - mined. the pdf flag is cleared when system power-up or executing the clr wdt instruction and is set when the halt instruction is executed. the to flag is set if the wdt time-out occurs, and causes a wake-up that only resets the program counter and stack pointer, the others keep their original status. on the other hand, awakening from an external interrupt (pc2), two sequences may happen. if the interrupt is disabled or the interrupt is enabled but the stack is full, the program will resume execution at the next instruc- tion. but if the interrupt is enabled and the stack is not full, the regular interrupt response takes place. the port a or port c [0:3] wake-up can be considered as a continuation of normal execution. each bit in port a can be independently selected to wake up the device by mask option. awakening from an i/o port stimulus, the program will resume execution of the next instruction. once a wake-up event occurs, and the system clock comes from a crystal, it takes 1024 t sys (system clock period) to resume normal operation. in other words, the device will insert a dummy period after the wake-up. if the system clock comes from an rc oscillator, it continues operating immediately. if the wake-up results in next instruction execution, this will execute immediately after the dummy period is completed. to minimize power consumption, all i/o pins should be carefully managed before entering the halt status.
ht82k68e-l/ht82k68a-l rev. 1.40 12 february 1, 2011 reset there are three ways in which a reset can occur: reset reset during normal operation reset reset during halt wdt time-out reset during normal operation the wdt time-out during halt is different from other chip reset conditions, since it can perform a warm reset that just resets the program counter and stack pointer, leaving the other circuits to remain in their original state. some registers remain unchanged during other reset conditions. most registers are reset to the initial condi - tion when the reset conditions are met. by examining the pdf and to flags, the program can distinguish be - tween different chip resets. to pdf reset conditions 0 0 reset reset during power-up u u reset reset during normal operation 0 0 reset wake-up halt 1 u wdt time-out during normal operation 1 1 wdt wake-up halt note: u means unchanged to guarantee that the system oscillator has started and stabilized, the sst (system start-up timer) provides an extra-delay of 1024 system clock pulses when the sys- tem powers up or when it awakes from the halt state. when a system power-up occurs, the sst delay is added during the reset period. but when the reset co- mes from the reset pin, the sst delay is disabled. any wake-up from halt will enable the sst delay. the functional unit chip reset status is shown below. program counter 000h prescaler clear wdt clear. after master reset, wdt begins counting timer counter off input/output ports input mode stack pointer points to the top of the stack timer counter a timer counter (tmr) is implemented in the microcontroller. the timer counter contains an 8-bit programmable count-up counter and the clock may come from the system clock divided by 4. using the internal instruction clock, there is only one ref - erence time-base. there are two registers related to the timer counter; tmr ([0dh]), tmrc ([0eh]). two physical registers are mapped to tmr location; writing tmr makes the start - ing value be placed in the timer counter preload register and reading tmr gets the contents of the timer counter. the tmrc is a timer counter control register, which de - fines some options. ' ; % ' ' reset timing chart reset circuit . . ; / ' > " $ a ;
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. ' reset configuration bit no. label function 0~3 unused bit, read as "0" 4 ton to enable/disable timer counting (0= disabled; 1= enabled) 5 unused bit, read as "0" 6 7 tm0 tm1 10= timer mode (internal clock) tmrc (0eh) register
ht82k68e-l/ht82k68a-l rev. 1.40 13 february 1, 2011 the state of the registers is summarized in the following table: register reset (power on) wdt time-out (normal operation) reset reset (normal operation) reset reset (halt) wdt time-out (halt) mp0 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu mp1 xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu acc xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu program counter 000h 000h 000h 000h 000h tblp xxxx xxxx uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu tblh -xxx xxxx -uuu uuuu -uuu uuuu -uuu uuuu -uuu uuuu wdts 0000 0111 0000 0111 0000 0111 0000 0111 uuuu uuuu status --00 xxxx --1u uuuu --uu uuuu --00 uuuu --11 uuuu intc -000 0000 -000 0000 -000 0000 -000 0000 -uuu uuuu tmr xxxx xxxx 0000 0000 0000 0000 0000 0000 uuuu uuuu tmrc 00-0 1--- 00-0 1--- 00-0 1--- 00-0 1--- uu-u u--- pa 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pac 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pb 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pbc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pcc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pd 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pdc 1111 1111 1111 1111 1111 1111 1111 1111 uuuu uuuu pe ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---u uuuu pec ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---u uuuu note: stands for warm reset u stands for unchanged x stands for unknown # ' / = , - / ' . %
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timer counter
ht82k68e-l/ht82k68a-l rev. 1.40 14 february 1, 2011 in the timer mode, once the timer counter starts count - ing, it will count from the current contents in the timer counter to ffh. once overflow occurs, the counter is re - loaded from the timer counter preload register and gen - erates the interrupt request flag (tf; bit 5 of intc) at the same time. to enable the counting operation, the timer on bit (ton; bit 4 of tmrc) should be set to 1. in the case of timer counter off condition, writing data to the timer counter preload register will also reload that data to the timer counter. but if the timer counter is turned on, data written to it will only be kept in the timer counter preload register. the timer counter will still operate until overflow occurs. when the timer counter (reading tmr) is read, the clock will be blocked to avoid errors. as clock blocking may results in a counting error, this must be taken into consideration by the programmer. input/output ports there are 34 bidirectional input/output lines in the microcontroller, labeled from pa to pe, which are mapped to the data memory of [12h], [14h], [16h], [18h] and [1ah] respectively. all these i/o ports can be used for input and output operations. for input operation, these ports are non-latching, that is, the inputs must be ready at the t2 rising edge of instruction mov a,[m] (m=12h, 14h, 16h, 18h or 1ah). for output operation, all data is latched and remains unchanged until the output latch is rewritten. each i/o line has its own control register (pac, pbc, pcc, pdc, pec) to control the input/output configura- tion. with this control register, cmos output or schmitt trigger input with or without pull-high resistor (mask op- tion) structures can be reconfigured dynamically (i.e., on-the-fly) under software control. to function as an input, the corresponding latch of the control register must write 1 . the pull-high resistance will exhibit automatically if the pull-high option is selected. the input source(s) also depend(s) on the control register. if the control register bit is 1 , input will read the pad state. if the control register bit is 0 , the contents of the latches will move to the internal bus. the latter is possible in read-modify-write instruc - tion. for output function, cmos is the only configuration. these control registers are mapped to locations 13h, 15h, 17h, 19h and 1bh. after a chip reset, these input/output lines stay at high levels or floating (mask option). each bit of these in - put/output latches can be set or cleared by the set [m].i or clr [m].i (m=12h, 14h, 16h, 18h or 1ah) instruction. some instructions first input data and then follow the output operations. for example, the set [m].i, clr [m].i, cpl [m] and cpla [m] instructions read the entire port states into the cpu, execute the defined operations (bit-operation), and then write the results back to the latches or the accumulator. each line of port a and port c [0:3] has the capability to wake-up the device. pc2 is shared with the external interrupt pin, pe2~pe4 is defined as cmos output pins only. pe0 can deter - mine whether the high to low transition, or the low to high transition of pc2 to activate the external subrou- tine, when pe0 output high, the low to high transition of pc2 to trigger the external subroutine, when pe0 output low, the high to low transition of pc2 to trigger the exter- nal subroutine. pe2~pe4 is configured as cmos output only and is used to drive the led. pc0, pc1 is configured as nmos open drain output with 4.6k pull-high resistor such that it can easy to use as data or clock line of ps2 keyboard application. d + d d + d ! ' 2 . '
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ht82k68e-l/ht82k68a-l rev. 1.40 15 february 1, 2011 low voltage reset lvr the microcontroller provides low voltage reset circuit in order to monitor the supply voltage of the device. if the supply voltage of the device is within the range 0.9v~v lvr such as changing a battery, the lvr will au - tomatically reset the device internally. the lvr includes the following specifications: the low voltage (0.9v~v lvr ) has to remain in their original state to exceed 1ms. if the low voltage state does not exceed 1ms, the lvr will ignore it and do not perform a reset function. the lvr uses the or function with the external res signal to perform chip reset. the relationship between v dd and v lvr is shown below. the relationship between v dd and v lvr is shown below. note: v opr is the voltage range for proper chip operation at 4mhz system clock. 4 c 4 $ c 8 '
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$ ' ' / low voltage reset note: *1: to make sure that the system oscillator has stabilized, the sst provides an extra delay of 1024 system clock pulses before entering the normal operation. *2: since low voltage has to be maintained in its original state and exceed 1ms, therefore 1ms delay enters the reset mode. 4 c 4 c $ c 8 c 4 c 4
application circuits rc oscillator for multiple i/o applications crystal oscillator or ceramic resonator for multiple i/o applications ht82k68e-l/ht82k68a-l rev. 1.40 16 february 1, 2011 " & * , - ' 6 '
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c 9 9 c 2 c " $ + $ + " " " " 3 - 4 5 ) 3 - 4 5 ) 0 8 3 - 4 5 ) " " " 3 " - " 4 " 5 " ) 2 2 2 2 3 2 - 2 4 2 5 2 ) 3 - 4 5 ) 5 ) " 3 - 4 5 ) 3 - 4 5 ) 0 8 3 - 4 5 ) " " " 3 " - " 4 " 5 " ) 2 2 2 2 3 2 - 2 4 2 5 2 ) 3 - 4 5 ) 5 ) c 9 9 9 c 2 c $ + $ + " " " " " - = - ) = c 9 - - 0 - ) = c 9 - - 0 rom code option the following shows six kinds of rom code option in the device. all the rom code options must be defined to ensure proper system function. no. rom code option 1 osc type selection. this option is to decide if an rc or crystal oscillator is chosen as system clock. if the crystal oscillator is selected, the xst (crystal start-up timer) default is activated, otherwise the xst is disabled. 2 wdt source selection. there are three types of selection: on-chip rc oscillator, instruction clock or disable the wdt. 3 clrwdt times selection. this option defines the way to clear the wdt by instruction. one time means that the clr wdt instruction can clear the wdt. two times means only if both of the clr wdt1 and clr wdt2 instructions have been executed, only then will the wdt be cleared. 4 wake-up selection. this option defines the wake-up function activity. external i/o pins (pa and pc [0:3] only) all have the capability to wake-up the chip from a halt. 5 pull-high selection. this option is to decide whether the pull-high resistance is visible or not in the input mode of the i/o ports. each bit of an i/o port can be independently selected. 6 lvr enable/disable. user can configure whether enable or disable the circuit by configuration option. 7 the input type only schmitt trigger input type can used for ht82k68e-l. the input type schmitt trigger input or inverter input type can used for ht82k68a-l.
ht82k68e-l/ht82k68a-l rev. 1.40 17 february 1, 2011 instruction set introduction central to the successful operation of any microcontroller is its instruction set, which is a set of pro - gram instruction codes that directs the microcontroller to perform certain operations. in the case of holtek microcontrollers, a comprehensive and flexible set of over 60 instructions is provided to enable programmers to implement their application with the minimum of pro - gramming overheads. for easier understanding of the various instruction codes, they have been subdivided into several func - tional groupings. instruction timing most instructions are implemented within one instruc - tion cycle. the exceptions to this are branch, call, or ta - ble read instructions where two instruction cycles are required. one instruction cycle is equal to 4 system clock cycles, therefore in the case of an 8mhz system oscillator, most instructions would be implemented within 0.5 s and branch or call instructions would be im - plemented within 1 s. although instructions which re - quire one more cycle to implement are generally limited to the jmp, call, ret, reti and table read instruc- tions, it is important to realize that any other instructions which involve manipulation of the program counter low register or pcl will also take one more cycle to imple- ment. as instructions which change the contents of the pcl will imply a direct jump to that new address, one more cycle will be required. examples of such instruc- tions would be clr pcl or mov pcl, a . for the case of skip instructions, it must be noted that if the re- sult of the comparison involves a skip operation then this will also take one more cycle, if no skip is involved then only one cycle is required. moving and transferring data the transfer of data within the microcontroller program is one of the most frequently used operations. making use of three kinds of mov instructions, data can be transferred from registers to the accumulator and vice-versa as well as being able to move specific imme - diate data directly into the accumulator. one of the most important data transfer applications is to receive data from the input ports and transfer data to the output ports. arithmetic operations the ability to perform certain arithmetic operations and data manipulation is a necessary feature of most microcontroller applications. within the holtek microcontroller instruction set are a range of add and subtract instruction mnemonics to enable the necessary arithmetic to be carried out. care must be taken to en - sure correct handling of carry and borrow data when re - sults exceed 255 for addition and less than 0 for subtraction. the increment and decrement instructions inc, inca, dec and deca provide a simple means of increasing or decreasing by a value of one of the values in the destination specified. logical and rotate operations the standard logical operations such as and, or, xor and cpl all have their own instruction within the holtek microcontroller instruction set. as with the case of most instructions involving data manipulation, data must pass through the accumulator which may involve additional programming steps. in all logical data operations, the zero flag may be set if the result of the operation is zero. another form of logical data manipulation comes from the rotate instructions such as rr, rl, rrc and rlc which provide a simple means of rotating one bit right or left. different rotate instructions exist depending on pro - gram requirements. rotate instructions are useful for serial port programming applications where data can be rotated from an internal register into the carry bit from where it can be examined and the necessary serial bit set high or low. another application where rotate data operations are used is to implement multiplication and division calculations. branches and control transfer program branching takes the form of either jumps to specified locations using the jmp instruction or to a sub- routine using the call instruction. they differ in the sense that in the case of a subroutine call, the program must return to the instruction immediately when the sub - routine has been carried out. this is done by placing a return instruction ret in the subroutine which will cause the program to jump back to the address right after the call instruction. in the case of a jmp instruction, the program simply jumps to the desired location. there is no requirement to jump back to the original jumping off point as in the case of the call instruction. one special and extremely useful set of branch instructions are the conditional branches. here a decision is first made re - garding the condition of a certain data memory or indi - vidual bits. depending upon the conditions, the program will continue with the next instruction or skip over it and jump to the following instruction. these instructions are the key to decision making and branching within the pro - gram perhaps determined by the condition of certain in - put switches or by the condition of internal data bits.
ht82k68e-l/ht82k68a-l rev. 1.40 18 february 1, 2011 bit operations the ability to provide single bit operations on data mem - ory is an extremely flexible feature of all holtek microcontrollers. this feature is especially useful for output port bit programming where individual bits or port pins can be directly set high or low using either the set [m].i or clr [m].i instructions respectively. the fea - ture removes the need for programmers to first read the 8-bit output port, manipulate the input data to ensure that other bits are not changed and then output the port with the correct new data. this read-modify-write pro - cess is taken care of automatically when these bit oper - ation instructions are used. table read operations data storage is normally implemented by using regis - ters. however, when working with large amounts of fixed data, the volume involved often makes it inconve - nient to store the fixed data in the data memory. to over - come this problem, holtek microcontrollers allow an area of program memory to be setup as a table where data can be directly stored. a set of easy to use instruc - tions provides the means by which this fixed data can be referenced and retrieved from the program memory. other operations in addition to the above functional instructions, a range of other instructions also exist such as the halt in - struction for power-down operations and instructions to control the operation of the watchdog timer for reliable program operations under extreme electric or electro - magnetic environments. for their relevant operations, refer to the functional related sections. instruction set summary the following table depicts a summary of the instruction set categorised according to function and can be con - sulted as a basic instruction reference using the follow - ing listed conventions. table conventions: x: bits immediate data m: data memory address a: accumulator i: 0~7 number of bits addr: program memory address mnemonic description cycles flag affected arithmetic add a,[m] addm a,[m] add a,x adc a,[m] adcm a,[m] sub a,x sub a,[m] subm a,[m] sbc a,[m] sbcm a,[m] daa [m] add data memory to acc add acc to data memory add immediate data to acc add data memory to acc with carry add acc to data memory with carry subtract immediate data from the acc subtract data memory from acc subtract data memory from acc with result in data memory subtract data memory from acc with carry subtract data memory from acc with carry, result in data memory decimal adjust acc for addition with result in data memory 1 1 note 1 1 1 note 1 1 1 note 1 1 note 1 note z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov z, c, ac, ov c logic operation and a,[m] or a,[m] xor a,[m] andm a,[m] orm a,[m] xorm a,[m] and a,x or a,x xor a,x cpl [m] cpla [m] logical and data memory to acc logical or data memory to acc logical xor data memory to acc logical and acc to data memory logical or acc to data memory logical xor acc to data memory logical and immediate data to acc logical or immediate data to acc logical xor immediate data to acc complement data memory complement data memory with result in acc 1 1 1 1 note 1 note 1 note 1 1 1 1 note 1 z z z z z z z z z z z increment & decrement inca [m] inc [m] deca [m] dec [m] increment data memory with result in acc increment data memory decrement data memory with result in acc decrement data memory 1 1 note 1 1 note z z z z
ht82k68e-l/ht82k68a-l rev. 1.40 19 february 1, 2011 mnemonic description cycles flag affected rotate rra [m] rr [m] rrca [m] rrc [m] rla [m] rl [m] rlca [m] rlc [m] rotate data memory right with result in acc rotate data memory right rotate data memory right through carry with result in acc rotate data memory right through carry rotate data memory left with result in acc rotate data memory left rotate data memory left through carry with result in acc rotate data memory left through carry 1 1 note 1 1 note 1 1 note 1 1 note none none c c none none c c data move mov a,[m] mov [m],a mov a,x move data memory to acc move acc to data memory move immediate data to acc 1 1 note 1 none none none bit operation clr [m].i set [m].i clear bit of data memory set bit of data memory 1 note 1 note none none branch jmp addr sz [m] sza [m] sz [m].i snz [m].i siz [m] sdz [m] siza [m] sdza [m] call addr ret ret a,x reti jump unconditionally skip if data memory is zero skip if data memory is zero with data movement to acc skip if bit i of data memory is zero skip if bit i of data memory is not zero skip if increment data memory is zero skip if decrement data memory is zero skip if increment data memory is zero with result in acc skip if decrement data memory is zero with result in acc subroutine call return from subroutine return from subroutine and load immediate data to acc return from interrupt 2 1 note 1 note 1 note 1 note 1 note 1 note 1 note 1 note 2 2 2 2 none none none none none none none none none none none none none table read tabrdc [m] tabrdl [m] read table (current page) to tblh and data memory read table (last page) to tblh and data memory 2 note 2 note none none miscellaneous nop clr [m] set [m] clr wdt clr wdt1 clr wdt2 swap [m] swapa [m] halt no operation clear data memory set data memory clear watchdog timer pre-clear watchdog timer pre-clear watchdog timer swap nibbles of data memory swap nibbles of data memory with result in acc enter power down mode 1 1 note 1 note 1 1 1 1 note 1 1 none none none to, pdf to, pdf to, pdf none none to, pdf note: 1. for skip instructions, if the result of the comparison involves a skip then two cycles are required, if no skip takes place only one cycle is required. 2. any instruction which changes the contents of the pcl will also require 2 cycles for execution. 3. for the clr wdt1 and clr wdt2 instructions the to and pdf flags may be affected by the execution status. the to and pdf flags are cleared after both clr wdt1 and clr wdt2 instructions are consecutively executed. otherwise the to and pdf flags remain unchanged.
instruction definition adc a,[m] add data memory to acc with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the accumulator. operation acc acc+[m]+c affected flag(s) ov, z, ac, c adcm a,[m] add acc to data memory with carry description the contents of the specified data memory, accumulator and the carry flag are added. the result is stored in the specified data memory. operation [m] acc+[m]+c affected flag(s) ov, z, ac, c add a,[m] add data memory to acc description the contents of the specified data memory and the accumulator are added. the result is stored in the accumulator. operation acc acc + [m] affected flag(s) ov, z, ac, c add a,x add immediate data to acc description the contents of the accumulator and the specified immediate data are added. the result is stored in the accumulator. operation acc acc+x affected flag(s) ov, z, ac, c addm a,[m] add acc to data memory description the contents of the specified data memory and the accumulator are added. the result is stored in the specified data memory. operation [m] acc + [m] affected flag(s) ov, z, ac, c and a,[m] logical and data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical and op - eration. the result is stored in the accumulator. operation acc acc and [m] affected flag(s) z and a,x logical and immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical and operation. the result is stored in the accumulator. operation acc acc and x affected flag(s) z andm a,[m] logical and acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical and op - eration. the result is stored in the data memory. operation [m] acc and [m] affected flag(s) z ht82k68e-l/ht82k68a-l rev. 1.40 20 february 1, 2011
call addr subroutine call description unconditionally calls a subroutine at the specified address. the program counter then in - crements by 1 to obtain the address of the next instruction which is then pushed onto the stack. the specified address is then loaded and the program continues execution from this new address. as this instruction requires an additional operation, it is a two cycle instruc - tion. operation stack program counter + 1 program counter addr affected flag(s) none clr [m] clear data memory description each bit of the specified data memory is cleared to 0. operation [m] 00h affected flag(s) none clr [m].i clear bit of data memory description bit i of the specified data memory is cleared to 0. operation [m].i 0 affected flag(s) none clr wdt clear watchdog timer description the to, pdf flags and the wdt are all cleared. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt1 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc- tion with clr wdt2 and must be executed alternately with clr wdt2 to have effect. re- petitively executing this instruction without alternately executing clr wdt2 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf clr wdt2 pre-clear watchdog timer description the to, pdf flags and the wdt are all cleared. note that this instruction works in conjunc - tion with clr wdt1 and must be executed alternately with clr wdt1 to have effect. re - petitively executing this instruction without alternately executing clr wdt1 will have no effect. operation wdt cleared to 0 pdf 0 affected flag(s) to, pdf ht82k68e-l/ht82k68a-l rev. 1.40 21 february 1, 2011
cpl [m] complement data memory description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. operation [m] [m] affected flag(s) z cpla [m] complement data memory with result in acc description each bit of the specified data memory is logically complemented (1 s complement). bits which previously contained a 1 are changed to 0 and vice versa. the complemented result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc [m] affected flag(s) z daa [m] decimal-adjust acc for addition with result in data memory description convert the contents of the accumulator value to a bcd ( binary coded decimal) value re - sulting from the previous addition of two bcd variables. if the low nibble is greater than 9 or if ac flag is set, then a value of 6 will be added to the low nibble. otherwise the low nibble remains unchanged. if the high nibble is greater than 9 or if the c flag is set, then a value of 6 will be added to the high nibble. essentially, the decimal conversion is performed by add - ing 00h, 06h, 60h or 66h depending on the accumulator and flag conditions. only the c flag may be affected by this instruction which indicates that if the original bcd sum is greater than 100, it allows multiple precision decimal addition. operation [m] acc + 00h or [m] acc + 06h or [m] acc + 60h or [m] acc + 66h affected flag(s) c dec [m] decrement data memory description data in the specified data memory is decremented by 1. operation [m] [m] 1 affected flag(s) z deca [m] decrement data memory with result in acc description data in the specified data memory is decremented by 1. the result is stored in the accu - mulator. the contents of the data memory remain unchanged. operation acc [m] 1 affected flag(s) z halt enter power down mode description this instruction stops the program execution and turns off the system clock. the contents of the data memory and registers are retained. the wdt and prescaler are cleared. the power down flag pdf is set and the wdt time-out flag to is cleared. operation to 0 pdf 1 affected flag(s) to, pdf ht82k68e-l/ht82k68a-l rev. 1.40 22 february 1, 2011
inc [m] increment data memory description data in the specified data memory is incremented by 1. operation [m] [m]+1 affected flag(s) z inca [m] increment data memory with result in acc description data in the specified data memory is incremented by 1. the result is stored in the accumu - lator. the contents of the data memory remain unchanged. operation acc [m]+1 affected flag(s) z jmp addr jump unconditionally description the contents of the program counter are replaced with the specified address. program execution then continues from this new address. as this requires the insertion of a dummy instruction while the new address is loaded, it is a two cycle instruction. operation program counter addr affected flag(s) none mov a,[m] move data memory to acc description the contents of the specified data memory are copied to the accumulator. operation acc [m] affected flag(s) none mov a,x move immediate data to acc description the immediate data specified is loaded into the accumulator. operation acc x affected flag(s) none mov [m],a move acc to data memory description the contents of the accumulator are copied to the specified data memory. operation [m] acc affected flag(s) none nop no operation description no operation is performed. execution continues with the next instruction. operation no operation affected flag(s) none or a,[m] logical or data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical or oper - ation. the result is stored in the accumulator. operation acc acc or [m] affected flag(s) z ht82k68e-l/ht82k68a-l rev. 1.40 23 february 1, 2011
or a,x logical or immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical or op - eration. the result is stored in the accumulator. operation acc acc or x affected flag(s) z orm a,[m] logical or acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical or oper - ation. the result is stored in the data memory. operation [m] acc or [m] affected flag(s) z ret return from subroutine description the program counter is restored from the stack. program execution continues at the re - stored address. operation program counter stack affected flag(s) none ret a,x return from subroutine and load immediate data to acc description the program counter is restored from the stack and the accumulator loaded with the specified immediate data. program execution continues at the restored address. operation program counter stack acc x affected flag(s) none reti return from interrupt description the program counter is restored from the stack and the interrupts are re-enabled by set- ting the emi bit. emi is the master interrupt global enable bit. if an interrupt was pending when the reti instruction is executed, the pending interrupt routine will be processed be- fore returning to the main program. operation program counter stack emi 1 affected flag(s) none rl [m] rotate data memory left description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 [m].7 affected flag(s) none rla [m] rotate data memory left with result in acc description the contents of the specified data memory are rotated left by 1 bit with bit 7 rotated into bit 0. the rotated result is stored in the accumulator and the contents of the data memory re - main unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 [m].7 affected flag(s) none ht82k68e-l/ht82k68a-l rev. 1.40 24 february 1, 2011
rlc [m] rotate data memory left through carry description the contents of the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into bit 0. operation [m].(i+1) [m].i; (i = 0~6) [m].0 c c [m].7 affected flag(s) c rlca [m] rotate data memory left through carry with result in acc description data in the specified data memory and the carry flag are rotated left by 1 bit. bit 7 replaces the carry bit and the original carry flag is rotated into the bit 0. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.(i+1) [m].i; (i = 0~6) acc.0 c c [m].7 affected flag(s) c rr [m] rotate data memory right description the contents of the specified data memory are rotated right by 1 bit with bit 0 rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 [m].0 affected flag(s) none rra [m] rotate data memory right with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit with bit 0 ro- tated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 [m].0 affected flag(s) none rrc [m] rotate data memory right through carry description the contents of the specified data memory and the carry flag are rotated right by 1 bit. bit 0 replaces the carry bit and the original carry flag is rotated into bit 7. operation [m].i [m].(i+1); (i = 0~6) [m].7 c c [m].0 affected flag(s) c rrca [m] rotate data memory right through carry with result in acc description data in the specified data memory and the carry flag are rotated right by 1 bit. bit 0 re - places the carry bit and the original carry flag is rotated into bit 7. the rotated result is stored in the accumulator and the contents of the data memory remain unchanged. operation acc.i [m].(i+1); (i = 0~6) acc.7 c c [m].0 affected flag(s) c ht82k68e-l/ht82k68a-l rev. 1.40 25 february 1, 2011
sbc a,[m] subtract data memory from acc with carry description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] c affected flag(s) ov, z, ac, c sbcm a,[m] subtract data memory from acc with carry and result in data memory description the contents of the specified data memory and the complement of the carry flag are sub - tracted from the accumulator. the result is stored in the data memory. note that if the re - sult of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] c affected flag(s) ov, z, ac, c sdz [m] skip if decrement data memory is 0 description the contents of the specified data memory are first decremented by 1. if the result is 0 the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m] 1 skip if [m] = 0 affected flag(s) none sdza [m] skip if decrement data memory is zero with result in acc description the contents of the specified data memory are first decremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in- struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation acc [m] 1 skip if acc = 0 affected flag(s) none set [m] set data memory description each bit of the specified data memory is set to 1. operation [m] ffh affected flag(s) none set [m].i set bit of data memory description bit i of the specified data memory is set to 1. operation [m].i 1 affected flag(s) none ht82k68e-l/ht82k68a-l rev. 1.40 26 february 1, 2011
siz [m] skip if increment data memory is 0 description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation [m] [m]+1 skip if [m] = 0 affected flag(s) none siza [m] skip if increment data memory is zero with result in acc description the contents of the specified data memory are first incremented by 1. if the result is 0, the following instruction is skipped. the result is stored in the accumulator but the specified data memory contents remain unchanged. as this requires the insertion of a dummy in - struction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m]+1 skip if acc = 0 affected flag(s) none snz [m].i skip if bit i of data memory is not 0 description if bit i of the specified data memory is not 0, the following instruction is skipped. as this re - quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is 0 the program proceeds with the following instruction. operation skip if [m].i 0 affected flag(s) none sub a,[m] subtract data memory from acc description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the accumulator. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc [m] affected flag(s) ov, z, ac, c subm a,[m] subtract data memory from acc with result in data memory description the specified data memory is subtracted from the contents of the accumulator. the result is stored in the data memory. note that if the result of subtraction is negative, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation [m] acc [m] affected flag(s) ov, z, ac, c sub a,x subtract immediate data from acc description the immediate data specified by the code is subtracted from the contents of the accumu - lator. the result is stored in the accumulator. note that if the result of subtraction is nega - tive, the c flag will be cleared to 0, otherwise if the result is positive or zero, the c flag will be set to 1. operation acc acc x affected flag(s) ov, z, ac, c ht82k68e-l/ht82k68a-l rev. 1.40 27 february 1, 2011
swap [m] swap nibbles of data memory description the low-order and high-order nibbles of the specified data memory are interchanged. operation [m].3~[m].0 [m].7 ~ [m].4 affected flag(s) none swapa [m] swap nibbles of data memory with result in acc description the low-order and high-order nibbles of the specified data memory are interchanged. the result is stored in the accumulator. the contents of the data memory remain unchanged. operation acc.3 ~ acc.0 [m].7 ~ [m].4 acc.7 ~ acc.4 [m].3 ~ [m].0 affected flag(s) none sz [m] skip if data memory is 0 description if the contents of the specified data memory is 0, the following instruction is skipped. as this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruc - tion. operation skip if [m] = 0 affected flag(s) none sza [m] skip if data memory is 0 with data movement to acc description the contents of the specified data memory are copied to the accumulator. if the value is zero, the following instruction is skipped. as this requires the insertion of a dummy instruc - tion while the next instruction is fetched, it is a two cycle instruction. if the result is not 0 the program proceeds with the following instruction. operation acc [m] skip if [m] = 0 affected flag(s) none sz [m].i skip if bit i of data memory is 0 description if bit i of the specified data memory is 0, the following instruction is skipped. as this re- quires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. if the result is not 0, the program proceeds with the following instruction. operation skip if [m].i = 0 affected flag(s) none tabrdc [m] read table (current page) to tblh and data memory description the low byte of the program code (current page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none tabrdl [m] read table (last page) to tblh and data memory description the low byte of the program code (last page) addressed by the table pointer (tblp) is moved to the specified data memory and the high byte moved to tblh. operation [m] program code (low byte) tblh program code (high byte) affected flag(s) none ht82k68e-l/ht82k68a-l rev. 1.40 28 february 1, 2011
xor a,[m] logical xor data memory to acc description data in the accumulator and the specified data memory perform a bitwise logical xor op - eration. the result is stored in the accumulator. operation acc acc xor [m] affected flag(s) z xorm a,[m] logical xor acc to data memory description data in the specified data memory and the accumulator perform a bitwise logical xor op - eration. the result is stored in the data memory. operation [m] acc xor [m] affected flag(s) z xor a,x logical xor immediate data to acc description data in the accumulator and the specified immediate data perform a bitwise logical xor operation. the result is stored in the accumulator. operation acc acc xor x affected flag(s) z ht82k68e-l/ht82k68a-l rev. 1.40 29 february 1, 2011
package information 20-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 0.419 b 0.256 0.300 c 0.012 0.020 c 0.496 0.512 d 0.104 e 0.050 f 0.004 0.012 g 0.016 0.050 h 0.008 0.013 08 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.62 c 0.30 0.51 c 12.60 13.00 d 2.64 e 1.27 f 0.10 0.30 g 0.41 1.27 h 0.20 0.33 08 ht82k68e-l/ht82k68a-l rev. 1.40 30 february 1, 2011 " 2 9 g >
28-pin sop (300mil) outline dimensions ms-013 symbol dimensions in inch min. nom. max. a 0.393 0.419 b 0.256 0.300 c 0.012 0.020 c 0.697 0.713 d 0.104 e 0.050 f 0.004 0.012 g 0.016 0.050 h 0.008 0.013 08 symbol dimensions in mm min. nom. max. a 9.98 10.64 b 6.50 7.62 c 0.30 0.51 c 17.70 18.11 d 2.64 e 1.27 f 0.10 0.30 g 0.41 1.27 h 0.20 0.33 08 ht82k68e-l/ht82k68a-l rev. 1.40 31 february 1, 2011 0 4 - " 2 9 g >
saw type 32-pin (5mm 5mm) qfn outline dimensions symbol dimensions in inch min. nom. max. a 0.028 0.031 a1 0.000 0.002 a3 0.008 b 0.007 0.012 d 0.197 e 0.197 e 0.020 d2 0.049 0.128 e2 0.049 0.128 l 0.012 0.020 k symbol dimensions in mm min. nom. max. a 0.70 0.80 a1 0.00 0.05 a3 0.20 b 0.18 0.30 d 5.00 e 5.00 e 0.50 d2 1.25 3.25 e2 1.25 3.25 l 0.30 0.50 k ht82k68e-l/ht82k68a-l rev. 1.40 32 february 1, 2011 1 " " 3 " $ + 0 8 5 ) - 4 3
48-pin ssop (300mil) outline dimensions symbol dimensions in inch min. nom. max. a 0.350 0.358 b 0.272 0.280 c 0.350 0.358 d 0.272 0.280 e 0.020 f 0.008 g 0.053 0.057 h 0.063 i 0.004 j 0.018 0.030 k 0.004 0.008 07 symbol dimensions in mm min. nom. max. a 8.90 9.10 b 6.90 7.10 c 8.90 9.10 d 6.90 7.10 e 0.50 f 0.20 g 1.35 1.45 h 1.60 i 0.10 j 0.45 0.75 k 0.10 0.20 07 ht82k68e-l/ht82k68a-l rev. 1.40 33 february 1, 2011 - 0 4 - " 2 9 g >
48-pin lqfp (7mm 7mm) outline dimensions symbol dimensions in inch min. nom. max. a 0.350 0.358 b 0.272 0.280 c 0.350 0.358 d 0.272 0.280 e 0.020 f 0.008 g 0.053 0.057 h 0.063 i 0.004 j 0.018 0.030 k 0.004 0.008 07 symbol dimensions in mm min. nom. max. a 8.90 9.10 b 6.90 7.10 c 8.90 9.10 d 6.90 7.10 e 0.50 f 0.20 g 1.35 1.45 h 1.60 i 0.10 j 0.45 0.75 k 0.10 0.20 07 ht82k68e-l/ht82k68a-l rev. 1.40 34 february 1, 2011 3 5 4 3 ) - 3 - 0 " 2 9 > h +
product tape and reel specifications reel dimensions sop 20w symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.20.2 sop 28w (300mil) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.01.5 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 24.8 +0.3/-0.2 t2 reel thickness 30.20.2 ht82k68e-l/ht82k68a-l rev. 1.40 35 february 1, 2011 " 2
saw type qfn 32-pin (5mm 5mm) symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.00.1 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 12.5 +0.3/-0.2 t2 reel thickness ssop 48w symbol description dimensions in mm a reel outer diameter 330.01.0 b reel inner diameter 100.00.1 c spindle hole diameter 13.0 +0.5/-0.2 d key slit width 2.00.5 t1 space between flange 32.2 +0.3/-0.2 t2 reel thickness 38.20.2 ht82k68e-l/ht82k68a-l rev. 1.40 36 february 1, 2011
carrier tape dimensions sop 20w symbol description dimensions in mm w carrier tape width 24.0 +0.3/-0.1 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.80.1 b0 cavity width 13.30.1 k0 cavity depth 3.20.1 t carrier tape thickness 0.300.05 c cover tape width 21.30.1 sop 28w (300mil) symbol description dimensions in mm w carrier tape width 24.00.3 p cavity pitch 12.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 11.50.1 d perforation diameter 1.5 +0.1/-0.0 d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 10.850.10 b0 cavity width 18.340.10 k0 cavity depth 2.970.10 t carrier tape thickness 0.350.01 c cover tape width 21.30.1 ht82k68e-l/ht82k68a-l rev. 1.40 37 february 1, 2011 . 9 + 2 " ' = '
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ssop 48w symbol description dimensions in mm w carrier tape width 32.00.3 p cavity pitch 16.00.1 e perforation position 1.750.10 f cavity to perforation (width direction) 14.20.1 d perforation diameter 2 min. d1 cavity hole diameter 1.50 +0.25/-0.00 p0 perforation pitch 4.00.1 p1 cavity to perforation (length direction) 2.00.1 a0 cavity length 12.00.1 b0 cavity width 16.20.1 k1 cavity depth 2.40.1 k2 cavity depth 3.20.1 t carrier tape thickness 0.350.05 c cover tape width 25.50.1 ht82k68e-l/ht82k68a-l rev. 1.40 38 february 1, 2011 9 + 2 " . + ' = '
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ht82k68e-l/ht82k68a-l rev. 1.40 39 february 1, 2011 copyright 2011 by holtek semiconductor inc. the information appearing in this data sheet is believed to be accurate at the time of publication. however, holtek as - sumes no responsibility arising from the use of the specifications described. the applications mentioned herein are used solely for the purpose of illustration and holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. holtek s products are not authorized for use as critical components in life support devices or systems. holtek reserves the right to alter its products without prior notification. for the most up-to-date information, please visit our web site at http://www.holtek.com.tw. holtek semiconductor inc. (headquarters) no.3, creation rd. ii, science park, hsinchu, taiwan tel: 886-3-563-1999 fax: 886-3-563-1189 http://www.holtek.com.tw holtek semiconductor inc. (taipei sales office) 4f-2, no. 3-2, yuanqu st., nankang software park, taipei 115, taiwan tel: 886-2-2655-7070 fax: 886-2-2655-7373 fax: 886-2-2655-7383 (international sales hotline) holtek semiconductor inc. (shenzhen sales office) 5f, unit a, productivity building, no.5 gaoxin m 2nd road, nanshan district, shenzhen, china 518057 tel: 86-755-8616-9908, 86-755-8616-9308 fax: 86-755-8616-9722 holtek semiconductor (usa), inc. (north america sales office) 46729 fremont blvd., fremont, ca 94538, usa tel: 1-510-252-9880 fax: 1-510-252-9885 http://www.holtek.com

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